US 12,387,799 B2
Semiconductor memory device
Yoshihiko Kamata, Yokohama (JP); and Naofumi Abiko, Kawasaki (JP)
Assigned to KIOXIA CORPORATION, Tokyo (JP)
Filed by KIOXIA CORPORATION, Tokyo (JP)
Filed on Oct. 6, 2023, as Appl. No. 18/482,103.
Application 18/482,103 is a continuation of application No. 17/807,034, filed on Jun. 15, 2022, granted, now 11,837,295.
Application 17/807,034 is a continuation of application No. 17/230,411, filed on Apr. 14, 2021, granted, now 11,393,545, issued on Jul. 19, 2022.
Application 17/230,411 is a continuation of application No. 16/220,878, filed on Dec. 14, 2018, granted, now 11,011,241, issued on May 18, 2021.
Application 16/220,878 is a continuation of application No. 15/886,464, filed on Feb. 1, 2018, granted, now 10,204,692, issued on Feb. 12, 2019.
Claims priority of application No. 2017-176641 (JP), filed on Sep. 14, 2017.
Prior Publication US 2024/0029805 A1, Jan. 25, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G11C 7/00 (2006.01); G11C 7/12 (2006.01); G11C 11/4094 (2006.01); G11C 11/56 (2006.01); G11C 16/04 (2006.01); G11C 16/08 (2006.01); G11C 16/24 (2006.01); G11C 16/26 (2006.01); G11C 16/32 (2006.01); G11C 16/34 (2006.01); G11C 7/18 (2006.01); G11C 8/08 (2006.01)
CPC G11C 16/3445 (2013.01) [G11C 7/12 (2013.01); G11C 11/4094 (2013.01); G11C 11/5635 (2013.01); G11C 16/0475 (2013.01); G11C 16/0483 (2013.01); G11C 16/08 (2013.01); G11C 16/24 (2013.01); G11C 16/26 (2013.01); G11C 16/32 (2013.01); G11C 16/3459 (2013.01); G11C 7/18 (2013.01); G11C 8/08 (2013.01); G11C 2211/5641 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first memory cell and a second memory cell;
a first word line connected to the first memory cell;
a second word line connected to the second memory cell;
a first sense amplifier and a second sense amplifier including a first transistor and a second transistor, respectively;
a first bit line connected between the first memory cell and the first transistor;
a second bit line connected between the second memory cell and the second transistor;
a controller configured to perform a first read operation and a second read operation;
a first conductor provided to extend in a first direction and to function as the first word line;
a second conductor provided to extend in the first direction and to function as the second word line;
a first pillar provided to extend through the first conductor in a second direction, an intersection between the first pillar and the first conductor functioning as the first memory cell;
a second pillar provided to extend through the second conductor in the second direction, an intersection between the second pillar and the second conductor functioning as the second memory cell;
a third pillar provided on the first conductor and electrically connected to the first conductor; and
a fourth pillar provided on the second conductor and electrically connected to the second conductor, wherein
the controller is further configured to apply a first voltage to a gate of the first transistor in the first read operation, and a second voltage lower than the first voltage to a gate of the second transistor in the second read operation.