US 12,387,777 B2
Refresh circuit and semiconductor memory device including the same
Jung Hwan Ji, Icheon-si (KR); Min Soo Park, Icheon-si (KR); and Geun Il Lee, Icheon-si (KR)
Assigned to SK hynix Inc., Icheon-si (KR)
Filed by SK hynix Inc., Icheon-si (KR)
Filed on Nov. 28, 2023, as Appl. No. 18/521,851.
Claims priority of application No. 10-2023-0084901 (KR), filed on Jun. 30, 2023.
Prior Publication US 2025/0006240 A1, Jan. 2, 2025
Int. Cl. G11C 11/406 (2006.01)
CPC G11C 11/40615 (2013.01) [G11C 11/406 (2013.01); G11C 11/40603 (2013.01)] 19 Claims
OG exemplary drawing
 
1. A refresh circuit configured to:
generate a counting signal by counting a refresh command,
generate a plurality of preliminary refresh cycle change signals by decoding the counting signal,
change a refresh cycle in response to one of the plurality of preliminary refresh cycle change signals, and
perform a refresh operation.