US 12,387,769 B2
Latency adjustment method, memory chip architecture, and semiconductor memory
Hongguang Zhang, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Jan. 19, 2023, as Appl. No. 18/156,461.
Application 18/156,461 is a continuation of application No. PCT/CN2022/100819, filed on Jun. 23, 2022.
Claims priority of application No. 202210563795.1 (CN), filed on May 23, 2022.
Prior Publication US 2023/0377620 A1, Nov. 23, 2023
Int. Cl. G11C 8/00 (2006.01); G11C 7/10 (2006.01); G11C 7/22 (2006.01)
CPC G11C 7/222 (2013.01) [G11C 7/1039 (2013.01); G11C 7/1093 (2013.01)] 17 Claims
OG exemplary drawing
 
1. A method for latency adjustment, comprising:
measuring a first latency of a first signal path;
performing decoding based on the first latency to obtain a number of latency cycles, wherein the number of latency cycles represents a ratio of the first latency to a clock cycle; and
controlling a second latency of a second signal path to be an integer multiple of the clock cycle based on the number of latency cycles;
wherein the second signal path comprises at least one load component, the second latency comprises an adjustable latency, and controlling the second latency of the second signal path to be the integer multiple of the clock cycle based on the number of latency cycles comprises:
based on the number of latency cycles, activating a first load component in the at least one load component, and changing an electric load value of the first load component to adjust the adjustable latency, so as to control the second latency to be the integer multiple of the clock cycle.