US 12,387,029 B2
Computing parasitic values for semiconductor designs
Akira Fujimura, Saratoga, CA (US); Nagesh Shirali, San Jose, CA (US); and Donald Oriordan, Sunnyvale, CA (US)
Assigned to D2S, INC., San Jose, CA (US)
Filed by D2S, Inc., San Jose, CA (US)
Filed on Aug. 16, 2022, as Appl. No. 17/889,370.
Application 17/889,370 is a continuation of application No. 17/871,893, filed on Jul. 22, 2022.
Claims priority of provisional application 63/203,455, filed on Jul. 23, 2021.
Prior Publication US 2023/0186009 A1, Jun. 15, 2023
Int. Cl. G06F 30/3953 (2020.01); G06F 30/27 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/045 (2023.01); G06T 7/00 (2017.01); G06F 119/06 (2020.01); G06F 119/10 (2020.01); H10D 86/40 (2025.01); H10D 86/60 (2025.01); H10D 89/60 (2025.01)
CPC G06F 30/3953 (2020.01) [G06F 30/27 (2020.01); G06F 30/392 (2020.01); G06F 30/398 (2020.01); G06N 3/045 (2023.01); G06T 7/0004 (2013.01); G06T 7/0006 (2013.01); G06F 2119/06 (2020.01); G06F 2119/10 (2020.01); G06T 2207/20084 (2013.01); G06T 2207/30121 (2013.01); G06T 2207/30148 (2013.01); H10D 86/441 (2025.01); H10D 86/60 (2025.01); H10D 89/60 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for calculating parasitic parameters for wire structures that are to be manufactured on a semiconductor substrate and that are to be defined in one or more semiconductor designs, the method comprising:
receiving a first wire structure that includes a plurality of rectilinear shapes associated with one or more semiconductor designs;
generating, from the first wire structure, a second wire structure comprising a plurality of curvilinear shapes; and
using the second wire structure to generate parasitic parameters for specifying parasitic effects experienced by one or more wire structures of the one or more semiconductor designs.