US 12,386,770 B2
Interface bus combining
Poojan Wagh, Sleepy Hollow, IL (US); and David A. Podsiadlo, San Diego, CA (US)
Assigned to pSemi Corporation, San Diego, CA (US)
Filed by pSemi Corporation, San Diego, CA (US)
Filed on Jan. 23, 2024, as Appl. No. 18/420,431.
Application 18/420,431 is a continuation of application No. 17/354,530, filed on Jun. 22, 2021, granted, now 11,886,228.
Prior Publication US 2024/0241849 A1, Jul. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/38 (2006.01); G06F 9/30 (2018.01); G06F 13/40 (2006.01); G06F 13/42 (2006.01)
CPC G06F 13/4027 (2013.01) [G06F 9/30101 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A circuit configured to be coupled to two or more buses, the circuit including:
(a) two or more agent devices;
(b) at least two decoders, each including:
(1) at least two common registers;
(2) a bus decoder coupled to the at least two common registers and configured to be coupled to a respective bus of the two or more buses, the bus decoder configured to assert a write-complete signal when a write operation to a corresponding one of the at least two common registers is completed;
(c) a first multiplexer having at least two selectable input bus ports, each selectable input bus port coupled to one of the at least two common registers within respective ones of the at least two decoders, and an output port configured to be coupled to at least one of the two or more agent devices;
(d) a second multiplexer having at least two selectable input bus ports, each selectable input bus port coupled to one of the at least two common registers within respective ones of the at least two decoders, and an output port configured to be coupled to at least one of the two or more agent devices; and
(e) a selection circuit, coupled to two or more of the bus decoders and to the first and second multiplexers, the selection circuit configured to select one of the at least two input bus ports of at least one of the first and second multiplexers in response to the assertion of a last write-complete signal from the coupled bus decoders.