US 12,386,768 B2
Extending multichip package link off package
Debendra Das Sharma, Saratoga, CA (US); Zuoguo Wu, San Jose, CA (US); Mahesh Wagh, Portland, OR (US); Mohiuddin M. Mazumder, San Jose, CA (US); Venkatraman Iyer, Austin, TX (US); and Jeff C. Morriss, Los Gatos, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Jul. 14, 2023, as Appl. No. 18/352,785.
Application 18/352,785 is a continuation of application No. 17/860,587, filed on Jul. 8, 2022, abandoned.
Application 17/860,587 is a continuation of application No. 17/121,534, filed on Dec. 14, 2020, granted, now 11,386,033, issued on Jul. 12, 2022.
Application 17/121,534 is a continuation of application No. 16/946,109, filed on Jun. 5, 2020, granted, now 11,113,225, issued on Sep. 7, 2021.
Application 16/946,109 is a continuation of application No. 15/761,401, granted, now 10,678,736, issued on Jun. 9, 2020, previously published as PCT/US2015/052160, filed on Sep. 25, 2015.
Prior Publication US 2024/0020259 A1, Jan. 18, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. G06F 13/40 (2006.01); G06F 13/42 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01)
CPC G06F 13/4027 (2013.01) [G06F 13/4022 (2013.01); G06F 13/405 (2013.01); G06F 13/4265 (2013.01); H01L 23/5386 (2013.01); H01L 25/0655 (2013.01); H01L 2224/16227 (2013.01); H01L 2924/15192 (2013.01); H01L 2924/15311 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An apparatus comprising:
a first die comprising:
a port to couple the first die to a second die over an interconnect, wherein the port comprises:
protocol circuitry to generate first data based on a first protocol and second data based on a different second protocol, wherein the first protocol comprises a first link layer and the second protocol comprises a different second link layer; and
physical layer circuitry to implement a physical layer of the interconnect, wherein the first data and the second data are to be sent on the physical layer from the first die to the second die, wherein the physical layer comprises a group of lanes comprising:
a valid lane;
a clock lane;
a plurality of data lanes; and
a sideband lane.