US 12,386,726 B2
Processor trace with suppression of periodic timing packets for low density trace sections
Markus Metzger, Ulm (DE); and Beeman Strong, Portland, OR (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Dec. 15, 2021, as Appl. No. 17/551,774.
Prior Publication US 2023/0185695 A1, Jun. 15, 2023
Int. Cl. G06F 11/00 (2006.01); G06F 11/362 (2025.01)
CPC G06F 11/3636 (2013.01) 15 Claims
OG exemplary drawing
 
1. An integrated circuit, comprising:
a processor; and
circuitry coupled to the processor, the circuitry to:
generate packets associated with a trace of an execution of code on the processor, the packets comprising:
a first plurality of packets which are each of a first timing packet type, wherein packets of the first timing packet type are to be generated on a periodic basis; and
a second plurality of packets which are each of a second timing packet type, wherein packets of the second timing packet type are to be generated each to provide a timestamp corresponding to a respective packet of a non-timing packet type;
identify a first event wherein a threshold number of multiple packets of the first plurality of packets are generated without any generation of an intervening packet of the non-timing packet type;
based on the first event, suppress generation of one or more of the first plurality of packets on the periodic basis during the trace;
resume generation of the one or more of the first plurality of packets on the periodic basis;
perform a calculation of a number of suppressed packets of the first timing packet type based on a difference between respective payload values of a first packet of the first plurality of packets and a respective immediately previous packet of the first plurality of packets; and
calculate a clock value based on the calculation of the number of suppressed packets of the first timing packet type.