US 12,386,543 B2
Opportunistic storage of non-write-boosted data in write booster cache memory
Giuseppe Cariello, Boise, ID (US); Jonathan S. Parry, Boise, ID (US); and Reshmi Basu, Boise, ID (US)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Nov. 9, 2023, as Appl. No. 18/505,661.
Claims priority of provisional application 63/387,536, filed on Dec. 15, 2022.
Prior Publication US 2024/0201888 A1, Jun. 20, 2024
Int. Cl. G06F 12/00 (2006.01); G06F 3/06 (2006.01)
CPC G06F 3/065 (2013.01) [G06F 3/0608 (2013.01); G06F 3/064 (2013.01); G06F 3/0679 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A memory device, comprising:
a non-volatile cache memory; and
one or more controllers configured to:
receive, from a host device, an indication of a threshold amount of the non-volatile cache memory to be reserved for first data for which write boosting is activated;
receive, from the host device, a write command that includes second data for which write boosting is deactivated;
determine that the second data is hot data;
identify a block of the non-volatile cache memory using a write boost cursor based on determining that the second data is hot data, based on the indication of the threshold amount, and despite write boosting being deactivated for the second data; and
write the second data to the block of the non-volatile cache memory.