US 12,386,506 B2
Tagged memory operated at lower VMIN in error tolerant system
Nitin Chawla, Noida (IN); Giuseppe Desoli, San Fermo della Battaglia (IT); Anuj Grover, New Delhi (IN); Thomas Boesch, Rovio (CH); Surinder Pal Singh, Noida (IN); and Manuj Ayodhyawasi, Noida (IN)
Assigned to STMICROELECTRONICS S.r.l., Argrate Brianza (IT); and STMicroelectronics International N.V., Geneva (CH)
Filed by STMICROELECTRONICS S.r.l., Agrate Brianza (IT); and STMicroelectronics International N.V., Geneva (CH)
Filed on Oct. 17, 2023, as Appl. No. 18/488,581.
Application 18/488,581 is a continuation of application No. 17/742,987, filed on May 12, 2022, granted, now 11,836,346.
Application 17/742,987 is a continuation of application No. 17/012,501, filed on Sep. 4, 2020, granted, now 11,360,667, issued on Jun. 14, 2022.
Claims priority of provisional application 62/897,937, filed on Sep. 9, 2019.
Prior Publication US 2024/0045589 A1, Feb. 8, 2024
Int. Cl. G06F 3/06 (2006.01); G06N 3/08 (2023.01)
CPC G06F 3/0604 (2013.01) [G06F 3/0619 (2013.01); G06F 3/0655 (2013.01); G06F 3/0679 (2013.01); G06N 3/08 (2013.01)] 22 Claims
OG exemplary drawing
 
1. A method of implementing an artificial neural network, the method comprising:
initiating performance of a process using a first subset of memory cells of a set of a memory cells of a memory array to store data at a first operational voltage that corresponds to a first operational accuracy of the process, wherein the set of memory cells of the memory array are arranged as a plurality of rows of memory cells intersecting a plurality of columns of memory cells and the first subset of memory cells includes a subset of columns in the plurality of columns of memory cells, a subset of rows in the plurality of rows of memory cells, or both a subset of columns in the plurality of columns of memory cells and a subset of rows in the plurality of rows of memory cells;
detecting an event associated with the process, wherein the event is a transition from processing associated with a first layer of the artificial neural network to processing associated with a second layer of the artificial neural network; and
in response to detection of the event, modifying the performance of the process to correspond to a second operational accuracy that is higher than the first operational accuracy, wherein the modifying the performance of the process includes:
providing, to the first subset of memory cells, a second operational voltage that is higher than the first operational voltage; or
initiating performance of the process using a second subset of memory cells of the set of memory cells of the memory array to store data at a third operational voltage that corresponds to the second operational accuracy of the process.