US 12,386,411 B2
Control device and data processing system
Haruki Katagiri, Kanagawa (JP); Kyoichi Mukao, Kanagawa (JP); Taiki Nonaka, Kanagawa (JP); Kazuhiko Fujita, Kanagawa (JP); and Yuta Ishikawa, Tokyo (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Appl. No. 17/781,172
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
PCT Filed Nov. 25, 2020, PCT No. PCT/IB2020/061110
§ 371(c)(1), (2) Date May 31, 2022,
PCT Pub. No. WO2021/111248, PCT Pub. Date Jun. 10, 2021.
Claims priority of application No. 2019-221483 (JP), filed on Dec. 6, 2019; and application No. 2020-038834 (JP), filed on Mar. 6, 2020.
Prior Publication US 2023/0004207 A1, Jan. 5, 2023
Int. Cl. G06F 1/3237 (2019.01); G06F 1/3203 (2019.01); G06F 1/3287 (2019.01); G06F 9/4401 (2018.01); G06F 21/32 (2013.01); G06V 40/12 (2022.01)
CPC G06F 1/3237 (2013.01) [G06F 21/32 (2013.01); G06V 40/1365 (2022.01); G06F 1/3203 (2013.01); G06F 1/3287 (2013.01); G06F 9/4418 (2013.01)] 4 Claims
OG exemplary drawing
 
1. A data processing system comprising:
a first housing, a second housing, an arithmetic circuit including a register and a cache for an arithmetic operation, an input unit including a sensor element, a power management unit, and a data processing unit,
wherein the arithmetic circuit, the input unit, and the power management unit are each at least partly positioned inside the first housing,
wherein the data processing unit is at least partly positioned inside the second housing,
wherein the power management unit is configured to control supply and shutdown of power to the arithmetic circuit,
wherein the sensor element includes one or more selected from an acceleration sensor, an angular velocity sensor, and a magnetic sensor,
wherein the register includes a first circuit and a second circuit,
wherein the register is configured to write first data in the first circuit in a first period during which the power management unit supplies power to the arithmetic circuit,
wherein the register is configured to write the first data in the second circuit in a second period during which the power management unit stops power supply to the arithmetic circuit,
wherein the second circuit is configured to retain the first data when supply of a clock signal is stopped,
wherein the arithmetic circuit is configured to generate second data with use of signal data output from the sensor element and the first data,
wherein the cache is configured to store and retain third data in the second period during which the power management unit stops power supply to the arithmetic circuit,
wherein the arithmetic circuit is configured to wirelessly transmit the second data and the third data to the data processing unit, and
wherein the data processing unit is configured to generate image data with use of the second data and the third data.