US 12,385,969 B2
Semiconductor device and semiconductor device testing method
Tomomi Miyano, Yokohama (JP)
Assigned to LAPIS Technology Co., Ltd., Yokohama (JP)
Filed by LAPIS Technology Co., Ltd., Yokohama (JP)
Filed on Sep. 5, 2023, as Appl. No. 18/461,463.
Claims priority of application No. 2022-143300 (JP), filed on Sep. 8, 2022.
Prior Publication US 2024/0085473 A1, Mar. 14, 2024
Int. Cl. G01R 31/28 (2006.01)
CPC G01R 31/2884 (2013.01) [G01R 31/2853 (2013.01); G01R 31/2896 (2013.01)] 14 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first semiconductor chip which includes a first internal circuit, a plurality of first flip-flop circuits connected to the first internal circuit, a plurality of first selectors, and a plurality of first electrodes connected to respective outputs of the plurality of first selectors;
a plurality of first connection conductors; and
a second semiconductor chip which includes a plurality of second electrodes respectively connected to the plurality of first electrodes via the plurality of first connection conductors and a second internal circuit connected to at least one of the plurality of second electrodes,
wherein at least one of the first semiconductor chip and the second semiconductor chip includes a part of a test circuit unit,
wherein the test circuit unit includes a first detection circuit which receives a signal from each of the plurality of second electrodes, a first selector control circuit which controls the plurality of first selectors, a first expected value generation circuit which generates a first expected value signal including a first expected value, and a test circuit which receives an output of the first detection circuit, and
wherein each of the plurality of first selectors includes a first signal input which receives a signal from any one of the plurality of first flip-flop circuits and a first expected value input which receives the first expected value signal from the first expected value generation circuit.