US 12,382,838 B2
Semiconductor memory device with spacer protection and method for forming same using multi-step patterning
Chih-Fan Huang, Kaohsiung (TW); Po-Sheng Lu, Hsinchu (TW); Chen-Chiu Huang, Taichung (TW); Dian-Hau Chen, Hsinchu (TW); and Yen-Ming Chen, Hsin-Chu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Nov. 11, 2021, as Appl. No. 17/524,041.
Claims priority of provisional application 63/185,439, filed on May 7, 2021.
Prior Publication US 2022/0359819 A1, Nov. 10, 2022
Int. Cl. H10N 50/01 (2023.01); H10B 61/00 (2023.01); H10N 50/80 (2023.01)
CPC H10N 50/01 (2023.02) [H10B 61/00 (2023.02); H10N 50/80 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a bottom electrode layer over a substrate;
forming a magnetic tunnel junction (MTJ) stack over the bottom electrode layer, the MTJ stack including a top magnetic layer, a barrier layer, and a bottom magnetic layer;
patterning the top magnetic layer in a first etch process;
after the patterning of the top magnetic layer, depositing a spacer on sidewalls of the patterned top magnetic layer; and
patterning the bottom magnetic layer and the bottom electrode layer in a second etch process, wherein after the second etch process sidewalls of the patterned bottom magnetic layer and the patterned bottom electrode layer are both exposed.