| CPC H10F 39/80373 (2025.01) [G01S 7/4863 (2013.01); H10F 39/014 (2025.01); H10F 39/18 (2025.01); H10F 39/805 (2025.01); H10F 39/8057 (2025.01); H10F 39/8063 (2025.01); H10F 39/807 (2025.01)] | 25 Claims |

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1. A light receiving element, comprising:
a semiconductor substrate;
a photoelectric conversion unit that is provided in the semiconductor substrate and that converts light into electric charges;
a first electric charge accumulation unit that is provided in the semiconductor substrate and to which the electric charges are transferred from the photoelectric conversion unit to the first charge accumulation unit;
a first distribution gate that is provided on a front surface of the semiconductor substrate and that distributes the electric charges from the photoelectric conversion unit to the first electric charge accumulation unit;
a second electric charge accumulation unit that is provided in the semiconductor substrate and to which the electric charges are transferred from the photoelectric conversion unit; and
a second distribution gate that is provided on the front surface of the semiconductor substrate and that distributes the electric charges from the photoelectric conversion unit to the second electric charge accumulation unit,
wherein the first and second distribution gates each have a pair of buried gate portions buried in the semiconductor substrate,
wherein the first and second distribution gates are provided so as to be substantially line-symmetric with respect to a center of the photoelectric conversion unit when viewed from above the front surface of the semiconductor substrate,
wherein the first and second electric charge accumulation units are provided so as to sandwich the first and second distribution gates therebetween,
wherein each of the buried gate portions has a substantially rectangular shape having a longer side extending in a direction from the center of the photoelectric conversion unit toward the first or second electric charge accumulation unit, in a cross section of the light receiving element taken along the front surface of the semiconductor substrate, and
wherein among the pair of buried gate portions, a side surface of one buried gate portion that is opposite to a side surface facing the other buried gate portion is in contact with a low dielectric layer.
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