US 12,382,714 B2
Memory devices and methods of manufacturing thereof
Meng-Sheng Chang, Chu-bei (TW); Chia-En Huang, Xinfeng Township (TW); and Yih Wang, Hsinchu (TW)
Assigned to Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsinchu (TW)
Filed on Jul. 25, 2022, as Appl. No. 17/872,885.
Application 17/872,885 is a division of application No. 16/786,521, filed on Feb. 10, 2020, granted, now 11,653,492.
Prior Publication US 2022/0367491 A1, Nov. 17, 2022
Int. Cl. H10D 84/83 (2025.01); H01L 21/02 (2006.01); H10B 20/20 (2023.01); H10B 20/25 (2023.01); H10D 30/00 (2025.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 62/40 (2025.01)
CPC H10D 84/834 (2025.01) [H01L 21/02433 (2013.01); H10B 20/20 (2023.02); H10B 20/25 (2023.02); H10D 30/024 (2025.01); H10D 30/501 (2025.01); H10D 30/62 (2025.01); H10D 62/121 (2025.01); H10D 62/405 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method for fabricating a semiconductor device, comprising:
forming a fin-based structure protruding from a substrate, wherein the fin-based structure is made of a first semiconductor material;
forming a first nanosheet-based structure protruding from the substrate, wherein the first nanosheet-based structure includes one or more first nanosheets, made of a second semiconductor material, and one or more second nanosheets, made of the first semiconductor material, the one or more first nanosheets and the one or more second nanosheets being alternatingly disposed with respect to each other; and
epitaxially growing a first source/drain (S/D) region, a second S/D region, and a third S/D region, wherein the first S/D region is disposed between the fin-based structure and the first nanosheet-based structure, the second S/D region is disposed opposite the fin-based structure from the first S/D region, and the third S/D region is disposed opposite the first nanosheet-based structure from the first S/D region, wherein sidewalls of the fin-based structure, functioning as active regions of a programming transistor, each has a {110} crystal plane, and a top boundary and a bottom boundary of each of the one or more first nanosheets, functioning as active regions of a reading transistor, have a {100} crystal plane, wherein the first to third S/D regions have a same conductive type.