US 12,382,711 B2
Semiconductor device
Shunsuke Asaba, Himeji Hyogo (JP); Hiroshi Kono, Himeji Hyogo (JP); and Makoto Mizukami, Ibo Hyogo (JP)
Assigned to Toshiba Electronic Devices & Storage Corporation, Tokyo (JP); and Kabushiki Kaisha Toshiba, Tokyo (JP)
Filed by TOSHIBA ELECTRONIC DEVICES & STORAGE CORPORATION, Tokyo (JP); and KABUSHIKI KAISHA TOSHIBA, Tokyo (JP)
Filed on Feb. 25, 2022, as Appl. No. 17/681,587.
Claims priority of application No. 2021-154471 (JP), filed on Sep. 22, 2021.
Prior Publication US 2023/0092735 A1, Mar. 23, 2023
Int. Cl. H10D 84/00 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01); H10D 62/832 (2025.01)
CPC H10D 84/146 (2025.01) [H10D 62/109 (2025.01); H10D 62/393 (2025.01); H10D 62/8325 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a silicon carbide layer having a first face and a second face facing the first face and including:
a first silicon carbide region of a first conductive type including a first region in contact with the first face;
a second silicon carbide region of a second conductive type provided between the first silicon carbide region and the first face;
a third silicon carbide region of the second conductive type provided between the second silicon carbide region and the first face and having a second conductive type impurity concentration higher than a second conductive type impurity concentration in the second silicon carbide region; and
a fourth silicon carbide region of the first conductive type provided between the second silicon carbide region and the first face and in contact with the first face;
a plurality of gate electrodes provided on a side of the first face of the silicon carbide layer, each of the plurality of gate electrodes extending in a first direction parallel to the first face, the plurality of gate electrodes being arranged in a second direction parallel to the first face and perpendicular to the first direction with separation from each other in the second direction, the plurality of gate electrodes including:
a first gate electrode facing the second silicon carbide region on the first face; and
a second gate electrode adjacent to the first gate electrode in the second direction, and facing the second silicon carbide region on the first face;
a first gate insulating layer provided between the second silicon carbide region and the first gate electrode;
a second gate insulating layer provided between the second silicon carbide region and the second gate electrode;
a first electrode provided on the side of the first face of the silicon carbide layer and including:
a first portion provided between the first gate electrode and the second gate electrode and in contact with the third silicon carbide region and the fourth silicon carbide region; and
a second portion provided between the first gate electrode and the second gate electrode, provided in the first direction of the first portion, and in contact with the first region; and
a second electrode provided on a side of the second face of the silicon carbide layer.