US 12,382,703 B2
Spacer features for nanosheet-based devices
I-Hsieh Wong, Hsinchu (TW); Alex Lee, Hsinchu (TW); Wei-Han Fan, Hsin-Chu (TW); Tzu-Hua Chiu, Hsinchu (TW); Wei-Yang Lee, Taipei (TW); and Chia-Pin Lin, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Company, Ltd., Hsin-Chu (TW)
Filed on Sep. 2, 2021, as Appl. No. 17/465,259.
Claims priority of provisional application 63/172,824, filed on Apr. 9, 2021.
Prior Publication US 2022/0328648 A1, Oct. 13, 2022
Int. Cl. H10D 64/66 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2006.01); H01L 21/764 (2006.01); H10D 30/01 (2025.01); H10D 30/67 (2025.01); H10D 62/10 (2025.01); H10D 64/01 (2025.01)
CPC H10D 64/679 (2025.01) [H01L 21/02211 (2013.01); H01L 21/0259 (2013.01); H01L 21/28123 (2013.01); H01L 21/764 (2013.01); H10D 30/031 (2025.01); H10D 30/6713 (2025.01); H10D 30/6735 (2025.01); H10D 30/6739 (2025.01); H10D 30/6757 (2025.01); H10D 62/118 (2025.01); H10D 64/018 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a base portion on a semiconductor substrate;
a channel layer vertically above the base portion and extending parallel to a top surface of the semiconductor substrate;
a gate portion between the channel layer and the base portion;
a source/drain feature connected to the channel layer;
an inner spacer between the source/drain feature and the gate portion, wherein the inner spacer includes a first spacer material in contact with the gate portion and a second spacer material spaced apart from the gate portion by the first spacer material, wherein a dielectric constant of the second spacer material is greater than a dielectric constant of the first spacer material; and
an air gap between the source/drain feature and the semiconductor substrate,
wherein a sidewall surface of the source/drain feature facing the inner spacer is entirely interfacing a dielectric material of the inner spacer without opening spaces,
wherein a bottom surface of the source/drain feature is exposed in the air gap.
 
9. A device, comprising:
a semiconductor substrate having a first surface;
base structures protruding vertically above the first surface;
a plurality of channel layers vertically arranged over the base structures;
gate portions between vertically adjacent channel layers;
inner spacers on sidewall surfaces of the gate portions, wherein each inner spacer has a first sublayer adjacent the gate portions and a second sublayer spaced apart from the gate portions and a dielectric constant of the second sublayer is greater than a dielectric constant of the first sublayer;
source/drain features on sidewall surfaces of the inner spacers and sidewall surfaces of the channel layers;
spacer layers on sidewall surfaces of the base structures and the first surface of the semiconductor substrate; and
air gaps defined by the spacer layers and the source/drain features.
 
15. A method, comprising:
receiving a semiconductor substrate having a stack of first semiconductor layers and second semiconductor layers thereon and a gate structure over the stack, the first semiconductor layers and the second semiconductor layers having different material compositions;
recessing the stack to form source/drain trenches on both sides of the gate structure and extending into the semiconductor substrate;
forming first spacers between end portions of vertically adjacent first semiconductor layers;
after the forming the first spacers, forming a blocking layer covering exposed surfaces of the semiconductor substrate; and
forming source/drain features from sidewall surfaces of the second semiconductor layers and away from the semiconductor substrate.