US 12,382,699 B2
Plasma-based barrier layer removal method for increasing peak transconductance while maintaining on-state resistance and related devices
Chris Hardiman, Morrisville, NC (US); Kyoung-Keun Lee, Cary, NC (US); Kyle Bothe, Cary, NC (US); and Fabian Radulescu, Chapel Hill, NC (US)
Assigned to MACOM TECHNOLOGY SOLUTIONS HOLDINGS, INC., Lowell, MA (US)
Filed by MACOM Technology Solutions Holdings, Inc., Lowell, MA (US)
Filed on Jun. 7, 2022, as Appl. No. 17/834,144.
Prior Publication US 2023/0395670 A1, Dec. 7, 2023
Int. Cl. H10D 64/27 (2025.01); H01L 21/285 (2006.01); H10D 30/01 (2025.01); H10D 30/47 (2025.01); H10D 62/824 (2025.01); H10D 62/85 (2025.01)
CPC H10D 64/411 (2025.01) [H01L 21/28581 (2013.01); H10D 30/015 (2025.01); H10D 30/475 (2025.01); H10D 62/824 (2025.01); H10D 62/8503 (2025.01)] 28 Claims
OG exemplary drawing
 
1. A transistor device, comprising:
a semiconductor structure comprising a channel layer and a barrier layer;
source and drain contacts on the semiconductor structure; and
a gate on the semiconductor structure between the source and drain contacts,
wherein a first portion of the barrier layer extending between the source or drain contact and the gate has a first thickness,
wherein a second portion of the barrier layer between the gate and the channel layer comprises a floor of a gate recess and has a second thickness, and
wherein the second thickness is less than a third thickness of the barrier layer at corner portions of the gate recess between the floor and opposing sidewalls of the gate recess.