US 12,382,694 B2
Radical etching in gate formation
Wei-Yu Tsai, Hsinchu (TW); Fu-Yao Nien, Hsinchu (TW); Hong-Wei Huang, Hsinchu (TW); and Chang-Sheng Lee, Hsin-Chu (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Aug. 5, 2021, as Appl. No. 17/395,195.
Application 17/395,195 is a division of application No. 16/573,552, filed on Sep. 17, 2019, granted, now 11,088,262.
Claims priority of provisional application 62/738,429, filed on Sep. 28, 2018.
Prior Publication US 2021/0376124 A1, Dec. 2, 2021
Int. Cl. H10D 64/01 (2025.01); H01L 21/02 (2006.01); H01L 21/28 (2025.01); H01L 21/3065 (2006.01); H10D 30/01 (2025.01); H10D 30/60 (2025.01); H10D 30/62 (2025.01); H10D 62/00 (2025.01); H10D 64/27 (2025.01)
CPC H10D 64/027 (2025.01) [H01L 21/02658 (2013.01); H01L 21/28114 (2013.01); H01L 21/3065 (2013.01); H10D 30/024 (2025.01); H10D 30/026 (2025.01); H10D 30/611 (2025.01); H10D 30/6211 (2025.01); H10D 30/6215 (2025.01); H10D 30/6217 (2025.01); H10D 30/6219 (2025.01); H10D 62/021 (2025.01); H10D 64/017 (2025.01); H10D 64/018 (2025.01); H10D 64/518 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor device, comprising:
a substrate;
a fin over the substrate, the fin including two source/drain regions and a channel region;
a gate structure engaging the channel region of the fin;
source/drain features on the source/drain regions of the fin;
a gate spacer between the gate structure and the source/drain features, the gate spacer having an inner sidewall interfacing the gate structure and an outer sidewall interfacing the source/drain features, the outer sidewall being lower than the inner sidewall; and
a dielectric layer over the source/drain features, wherein a top surface of the dielectric layer has a recess that is lower than the outer sidewall.