| CPC H10D 62/151 (2025.01) [H10D 30/43 (2025.01); H10D 30/6729 (2025.01); H10D 30/6735 (2025.01); H10D 62/121 (2025.01); H10D 62/834 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
an active region extending in a first direction on a substrate;
a plurality of channel layers disposed to be spaced apart from each other in a vertical direction, perpendicular to an upper surface of the substrate, on the active region;
a gate structure extending in a second direction perpendicular to the first direction to intersect the active region and the plurality of channel layers on the substrate and surrounding each of the plurality of channel layers;
a source/drain region disposed on the active region on at least one side of the gate structure and contacting the plurality of channel layers; and
a contact plug connected to the source/drain region,
wherein the source/drain region comprises:
a first epitaxial layer disposed on the active region and extending to contact the plurality of channel layers;
second epitaxial layers disposed on the first epitaxial layer, each second epitaxial layer including impurities in a first concentration and having a first thickness; and
doping layers stacked alternately with the second epitaxial layers, each doping layer including impurities in a second concentration higher than the first concentration and having a second thickness less than the first thickness,
wherein side surfaces of each of the second epitaxial layers and each of the doping layers contact the first epitaxial layer, and
wherein the contact plug contacts at least a portion of the doping layers.
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