US 12,382,682 B2
Gate-all-around nanosheet-FET with variable channel geometries for performance optimization
Julien Frougier, Albany, NY (US); Ruilong Xie, Niskayuna, NY (US); Heng Wu, Guilderland, NY (US); Chen Zhang, Guilderland, NY (US); and Alexander Reznicek, Troy, NY (US)
Assigned to International Business Machines Corporation, Armonk, NY (US)
Filed by INTERNATIONAL BUSINESS MACHINES CORPORATION, Armonk, NY (US)
Filed on Nov. 8, 2021, as Appl. No. 17/453,882.
Prior Publication US 2023/0142410 A1, May 11, 2023
Int. Cl. H10D 62/10 (2025.01); H10D 30/01 (2025.01); H10D 30/43 (2025.01); H10D 30/67 (2025.01); H10D 64/01 (2025.01)
CPC H10D 62/121 (2025.01) [H10D 30/014 (2025.01); H10D 30/43 (2025.01); H10D 30/6735 (2025.01); H10D 30/6757 (2025.01); H10D 64/017 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor device comprising:
a first nanosheet having a tapered profile in the Y-direction to have a width W1 and the first nanosheet is tapered in the X-direction to have a length L1, wherein the tapered profile in the Y-direction is at a first angle and the tapered profile in the X-direction is at a second angle;
a second nanosheet having a tapered fin profile in the Y-direction to have a width W2 and the first nanosheet is tapered in the X-direction to have a length L2, wherein the tapered profile in the Y-direction is at the first angle and the tapered profile in the X-direction is at the second angle, wherein the first angle and the second angle are different;
a bottom dielectric isolation layer located beneath the first and second nanosheets, wherein the bottom dielectric isolation layer has a tapered profile in the Y-direction and a different profile in the X-direction; and
wherein the widths W1 and W2 are different from each other and the lengths L1 and L2 are different from each other.