| CPC H10D 62/112 (2025.01) [H10D 30/6735 (2025.01); H10D 62/115 (2025.01); H10D 62/118 (2025.01); H10D 62/121 (2025.01); H10D 64/518 (2025.01); H10D 30/026 (2025.01); H10D 30/031 (2025.01); H10D 30/6757 (2025.01); H10D 64/258 (2025.01)] | 20 Claims |
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1. A semiconductor device comprising:
an active pattern provided on a substrate having an upper surface that extends in a first direction and a second direction that crosses the first direction, the active pattern extending in the first direction;
an isolation pattern provided on the substrate between the active pattern and an adjacent active pattern;
an insulation pattern provided above the substrate and contacting an upper surface of the active pattern, the insulation pattern extending beyond a sidewall of the active pattern in the second direction to an upper surface of the isolation pattern;
channels spaced apart from each other along a third direction perpendicular to the upper surface of the substrate, each of the channels extending in the first direction and comprising a material provided in the active pattern; and
a gate structure contacting an upper surface of the insulation pattern, an upper surface of the channels, a lower surface of the channels, and sidewalls of the channels opposite to each other along the second direction, the gate structure extending in the second direction,
wherein a first distance between an upper surface of the active pattern and a lowermost one of the channels is greater than a second distance between an upper surface of one of the channels and a lower surface of an adjacent channel.
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