US 12,382,679 B2
Semiconductor device and manufacturing method
Ming Qiao, Chengdu (CN); Ruidi Wang, Chengdu (CN); Yibing Wang, Chengdu (CN); Wenyang Bai, Chengdu (CN); and Bo Zhang, Chengdu (CN)
Assigned to University of Electronic Science and Technology of China, Chengdu (CN); and Institute of Electronic and Information Engineering of UESTC in Guangdong, Dongguan (CN)
Filed by University of Electronic Science and Technology of China, Chengdu (CN); and Institute of Electronic and Information Engineering of UESTC in Guangdong, Dongguan (CN)
Filed on Jun. 3, 2022, as Appl. No. 17/831,454.
Claims priority of application No. 202111254973.4 (CN), filed on Oct. 27, 2021.
Prior Publication US 2023/0129440 A1, Apr. 27, 2023
Int. Cl. H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/761 (2006.01); H10D 30/01 (2025.01); H10D 30/66 (2025.01); H10D 62/10 (2025.01); H10D 62/17 (2025.01)
CPC H10D 62/111 (2025.01) [H01L 21/26513 (2013.01); H01L 21/266 (2013.01); H01L 21/761 (2013.01); H10D 30/0291 (2025.01); H10D 30/66 (2025.01); H10D 62/393 (2025.01)] 18 Claims
OG exemplary drawing
 
1. A manufacturing method of a semiconductor device, comprising:
step 1: providing a first type substrate;
step 2: forming a first type buffer layer on an upper surface of the first type substrate;
step 3: forming a first first-type epitaxial layer on an upper surface of the first type buffer layer, and etching with a first mask to obtain alternately arranged trench structures;
step 4: filling the alternately arranged trench structures with a second type semiconductor material and polishing to obtain a plurality of first type drift regions and second type compensation regions;
step 5: forming a second first-type epitaxial layer on surfaces of the plurality of first type drift regions and the second type compensation regions, and performing a first ion implantation to adjust a concentration of the second first-type epitaxial layer;
step 6: forming second type modulation regions on an upper surface of the second first-type epitaxial layer by a second ion implantation with a second mask;
step 7: forming a third first-type epitaxial layer on an upper surface of a first type modulation region, and performing a third ion implantation to adjust a concentration of the third first-type epitaxial layer;
step 8: forming a dielectric material on the upper surface of the third first-type epitaxial layer, and depositing a gate electrode material on an upper surface of the dielectric layer;
step 9: forming a gate dielectric and a gate electrode by etching with a third mask;
step 10: performing a fourth ion implantation by a self-aligned technique;
step 11: forming second type body regions by annealing;
step 12: forming first type source regions by a fifth ion implantation on upper surfaces of the second type body regions with a fourth mask;
step 13: depositing a passivation layer on an upper surface of the semiconductor device, and etching with a fifth mask to obtain a source contact hole;
step 14: forming second type body contact regions by a sixth ion implantation;
step 15: forming a source electrode on the upper surface of the semiconductor device;
wherein the semiconductor device obtained by the above steps comprises:
the first type substrate;
the first type buffer layer is located above the first type substrate;
the plurality of first type drift regions and the second type compensation regions are alternately arranged above the first type buffer layer;
the first type modulation region is located above the plurality of first type drift regions;
the second type modulation regions are located above the second type compensation regions;
a plurality of body structures are located above the second type modulation region;
the plurality of body structures comprise a second type body region, a first type source region, and a second type body contact region;
a first type neck region is located between two adjacent body structures;
a gate structure is located above the upper surface of the semiconductor device;
the gate structure comprises the gate dielectric and the gate electrode located above an upper surface of the gate dielectric;
the passivation layer is located above the gate structure; and
the source electrode is deposited on the gate structure contacting the first type source region and the second type body contact region.