US 12,382,678 B2
Transistor arrangement with a lateral superjunction transistor device
Rolf Weis, Dresden (DE); Franz Hirler, Isen (DE); Katarzyna Kowalik-Seidl, Unterhaching (DE); Marco Mueller, Pirna (DE); and Anthony Sanders, Weißenfeld (DE)
Assigned to Infineon Technologies Dresden GmbH & Co. KG, Dresden (DE)
Filed by Infineon Technologies Dresden GmbH & Co. KG, Dresden (DE)
Filed on May 17, 2022, as Appl. No. 17/745,946.
Claims priority of application No. 21176031 (EP), filed on May 26, 2021.
Prior Publication US 2022/0384567 A1, Dec. 1, 2022
Int. Cl. H10D 62/10 (2025.01); H10D 30/83 (2025.01); H10D 62/17 (2025.01); H10D 84/84 (2025.01)
CPC H10D 62/111 (2025.01) [H10D 30/83 (2025.01); H10D 62/343 (2025.01); H10D 84/84 (2025.01)] 12 Claims
OG exemplary drawing
 
1. A transistor arrangement, comprising:
a first transistor device; and
a second transistor device,
wherein the first transistor device and the second transistor device are connected in series and integrated in a common semiconductor body,
wherein the first transistor device is a lateral superjunction transistor device and is integrated in a first device region of the semiconductor body,
wherein the second transistor device is a lateral transistor device and is integrated in at least one second device region of the semiconductor body,
wherein the at least one second device region is spaced apart from the first device region.