US 12,382,677 B2
Power semiconductor device having nanometer-scale structure
Anton Mauder, Kolbermoor (DE); Franz-Josef Niedernostheide, Hagen am Teutoburger Wald (DE); and Christian Philipp Sandow, Haar (DE)
Assigned to Infineon Technologies AG, Neubiberg (DE)
Filed by Infineon Technologies AG, Neubiberg (DE)
Filed on Nov. 5, 2021, as Appl. No. 17/519,737.
Application 17/519,737 is a division of application No. 16/410,293, filed on May 13, 2019, granted, now 11,171,202.
Application 16/410,293 is a continuation of application No. 15/637,459, filed on Jun. 29, 2017, granted, now 10,340,336, issued on Jul. 2, 2019.
Claims priority of application No. 102016112016.2 (DE), filed on Jun. 30, 2016.
Prior Publication US 2022/0059650 A1, Feb. 24, 2022
Int. Cl. H10D 62/10 (2025.01); H10D 12/00 (2025.01); H10D 30/66 (2025.01); H10D 84/00 (2025.01)
CPC H10D 62/111 (2025.01) [H10D 12/481 (2025.01); H10D 84/141 (2025.01); H10D 84/161 (2025.01); H10D 30/668 (2025.01); H10D 62/106 (2025.01); H10D 62/127 (2025.01)] 14 Claims
OG exemplary drawing
 
1. A power semiconductor device, comprising:
a semiconductor body coupled to a first load terminal structure and a second load terminal structure;
an active cell field implemented in the semiconductor body and configured to conduct a load current;
a plurality of first cells and a plurality of second cells provided in the active cell field, each being electrically connected to the first load terminal structure on one side and electrically connected to a drift region of the semiconductor body on another side, the drift region having a first conductivity type;
a first plateau region disposed in the semiconductor body and having the first conductivity type;
wherein:
each first cell comprises a first mesa, the first mesa including: a first port region having the first conductivity type and being electrically connected to the first load terminal structure, a first channel region being coupled to the drift region, and a first control electrode that is configured to induce a current path for charge carriers of the first conductivity type within the first channel region;
each second cell comprises a second mesa, the second mesa including: a second port region having a second conductivity type and being electrically connected to the first load terminal structure, a second channel region being coupled to the drift region, and a second control electrode that is configured to induce a current path for charge carriers of the second conductivity type within the second channel region;
the first plateau region is in contact with the first channel region at an upper side within the first mesa and interfaces with the drift region at a lower side and below the first mesa,
a dopant concentration of the first plateau region is higher than a dopant concentration of the drift zone,
wherein the first and second port regions each extend to an upper surface of the semiconductor body,
wherein the current path for charge carriers of the second conductivity type flows through the second port region,
wherein at a location within the semiconductor body that is vertically below the first and second control electrodes, the first plateau region laterally extends across the first control electrode to an edge of the first plateau region between the first control electrode and the second control electrode.