US 12,382,672 B2
Epitaxial wafer and semiconductor memory device using the same
Junga Lee, Suwon-si (KR); Yeonsook Kim, Hwaseong-si (KR); and Wooseung Jung, Busan (KR)
Assigned to SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed by SAMSUNG ELECTRONICS CO., LTD., Suwon-si (KR)
Filed on Oct. 31, 2022, as Appl. No. 17/977,013.
Claims priority of application No. 10-2021-0153445 (KR), filed on Nov. 9, 2021.
Prior Publication US 2023/0141135 A1, May 11, 2023
Int. Cl. H10D 30/69 (2025.01); H10B 12/00 (2023.01); H10D 62/815 (2025.01)
CPC H10D 30/792 (2025.01) [H10B 12/30 (2023.02); H10D 62/8164 (2025.01)] 19 Claims
OG exemplary drawing
 
1. An epitaxial wafer, comprising:
a semiconductor substrate having a front surface and a rear surface opposite to each other;
a strain relaxed buffer (SRB) layer on and entirely covering the front surface of the semiconductor substrate; and
a multi-stack on and entirely covering a surface of the SRB layer,
wherein:
the SRB layer includes a silicon germanium (SiGe) epitaxial layer including germanium (Ge) at a first concentration of about 2.5 at % to about 18 at %, wherein the first concentration is an amount that causes a lattice constant of the SRB layer to be between a lattice constant of the semiconductor substrate and an overall lattice constant of the multi-stack,
the multi-stack has a superlattice structure in which a plurality of silicon (Si) layers and a plurality of SiGe layers are alternately provided, and
the overall lattice constant is an effective lattice constant of the multi-stack that depends at least on:
a thickness of a respective Si layer of the plurality of Si layers;
a thickness of a respective SiGe layer of the plurality of SiGe layers;
a lattice constant of the respective Si layer; and
a lattice constant of the respective SiGe layer.