| CPC H10D 30/701 (2025.01) [H01L 21/02181 (2013.01); H01L 21/0228 (2013.01); H01L 21/02356 (2013.01); H10D 30/024 (2025.01); H10D 30/0415 (2025.01); H10D 30/62 (2025.01); H10D 30/791 (2025.01); H10D 62/121 (2025.01); H10D 64/017 (2025.01); H10D 64/689 (2025.01); H10D 64/691 (2025.01)] | 20 Claims |

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1. A semiconductor device, comprising:
a metal gate layer over a substrate; and
a channel between a source region and a drain region in the substrate;
a ferroelectric layer, disposed between the metal gate layer and the substrate, wherein the ferroelectric layer comprises hafnium oxide-based material, wherein the ferroelectric layer is configured to cause a strain in the channel when applied with an electric field, the hafnium oxide-based material comprises:
a first portion of hafnium oxide with orthorhombic phase, a second portion of hafnium oxide with monoclinic phase, and a third portion of the hafnium oxide with tetragonal phase.
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