	US 12,382,664 B2
	Semiconductor device
Kazuya Hanaoka, Kanagawa (JP); Daisuke Matsubayashi, Kanagawa (JP); Yoshiyuki Kobayashi, Kanagawa (JP); Shunpei Yamazaki, Tokyo (JP); and Shinpei Matsuda, Kanagawa (JP)
Assigned to Semiconductor Energy Laboratory Co., Ltd., Kanagawa-ken (JP)
Filed by SEMICONDUCTOR ENERGY LABORATORY CO., LTD., Atsugi (JP)
Filed on Apr. 4, 2024, as Appl. No. 18/626,777.
Application 18/626,777 is a continuation of application No. 17/844,767, filed on Jun. 21, 2022, granted, now 11,961,917, issued on Apr. 16, 2024.
Application 17/844,767 is a continuation of application No. 16/710,456, filed on Dec. 11, 2019, granted, now 11,430,894, issued on Aug. 30, 2022.
Application 16/710,456 is a continuation of application No. 15/617,696, filed on Jun. 8, 2017, granted, now 10,573,758, issued on Feb. 25, 2020.
Application 15/617,696 is a continuation of application No. 14/277,465, filed on May 14, 2014, granted, now 9,722,088, issued on Aug. 1, 2017.
Claims priority of application No. 2013-106284 (JP), filed on May 20, 2013; application No. 2013-147191 (JP), filed on Jul. 16, 2013; application No. 2013-196300 (JP), filed on Sep. 23, 2013; and application No. 2014-087067 (JP), filed on Apr. 21, 2014.
Prior Publication US 2024/0355930 A1, Oct. 24, 2024
Int. Cl. H10D 30/67 (2025.01); H10D 30/62 (2025.01)

CPC H10D 30/6755 (2025.01) [H10D 30/6729 (2025.01); H10D 30/6757 (2025.01); H10D 30/62 (2025.01); H10D 30/6213 (2025.01)]

3 Claims

1. A semiconductor device comprising:

a first transistor comprising silicon in a first channel formation region; and

a second transistor over the first transistor, the second transistor comprising an oxide semiconductor in a second channel formation region,

wherein a first insulating layer is provided over the first channel formation region,

wherein a first gate electrode of the first transistor is provided over the first insulating layer,

wherein a second insulating layer is provided over the first gate electrode of the first transistor,

wherein a second gate electrode of the second transistor is provided over the second insulating layer,

wherein a third insulating layer is provided over the second gate electrode of the second transistor,

wherein a layer comprising the second channel formation region is provided over the third insulating layer,

wherein a fourth insulating layer is provided over the layer comprising the second channel formation region,

wherein a third gate electrode of the second transistor is provided over the fourth insulating layer,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to one of a source electrode and a drain electrode of the second transistor via a first opening provided in the second insulating layer and a second opening provided in the third insulating layer,

wherein the one of the source electrode and the drain electrode of the second transistor is in contact with a top surface of the layer comprising the second channel formation region,

wherein a first conductive layer is provided over a fifth insulating layer and a sixth insulating layer,

wherein the first conductive layer overlaps with the third gate electrode of the second transistor,

wherein the first conductive layer overlaps with a second conductive layer,

wherein the second conductive layer is electrically connected to the first gate electrode of the first transistor,

wherein the second conductive layer overlaps with a third conductive layer, and

wherein the third conductive layer overlaps with the first gate electrode of the first transistor.