US 12,382,655 B2
Transistors having vertical nanostructures
Pei-Hsun Wang, Hsinchu (TW); Chun-Hsiung Lin, Hsinchu County (TW); Cheng-Ting Chung, Hsinchu (TW); and Chih-Hao Wang, Hsinchu County (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsinchu (TW)
Filed on Jul. 28, 2023, as Appl. No. 18/361,491.
Application 18/361,491 is a continuation of application No. 17/133,290, filed on Dec. 23, 2020, granted, now 11,777,033.
Claims priority of provisional application 62/982,610, filed on Feb. 27, 2020.
Prior Publication US 2023/0378363 A1, Nov. 23, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H01L 29/78 (2006.01); H01L 21/8234 (2006.01); H01L 29/06 (2006.01); H01L 29/66 (2006.01); H10D 30/01 (2025.01); H10D 30/62 (2025.01); H10D 62/10 (2025.01); H10D 84/01 (2025.01); H10D 84/03 (2025.01)
CPC H10D 30/6211 (2025.01) [H10D 30/024 (2025.01); H10D 62/116 (2025.01); H10D 62/118 (2025.01); H10D 84/0128 (2025.01); H10D 84/013 (2025.01); H10D 84/0158 (2025.01); H10D 84/038 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a fin structure rising from a substrate;
a first isolation feature disposed over a top surface of the substrate and along a first sidewall of the fin structure;
a second isolation feature disposed over the top surface of the substrate and along a second sidewall of the fin structure, the second sidewall being opposed to the first sidewall;
a first channel member and a second channel member disposed over the first isolation feature;
a third channel member and a fourth channel member disposed over the second isolation feature; and
a gate structure wrapping over the first channel member, the second channel member, the third channel member, and the fourth channel member,
wherein a top surface of the fin structure is lower than top surfaces of the first isolation feature and the second isolation feature.