US 12,382,649 B2
Semiconductor device and forming method thereof
Feng Han, Shanghai (CN); Jian Huang, Shanghai (CN); Lin-Chun Gui, Shanghai (CN); and Zhong-Hao Chen, Shanghai (CN)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY LIMITED, Shanghai (CN)
Filed by TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW); and TSMC CHINA COMPANY LIMITED, Shanghai (CN)
Filed on Mar. 26, 2021, as Appl. No. 17/214,443.
Claims priority of application No. 202011548021.9 (CN), filed on Dec. 23, 2020.
Prior Publication US 2022/0199803 A1, Jun. 23, 2022
Int. Cl. H10D 30/01 (2025.01); H01L 21/265 (2006.01); H01L 21/266 (2006.01); H01L 21/28 (2006.01); H01L 21/285 (2006.01); H10D 30/60 (2025.01); H10D 64/62 (2025.01); H10D 64/66 (2025.01)
CPC H10D 30/022 (2025.01) [H01L 21/26513 (2013.01); H01L 21/266 (2013.01); H01L 21/28052 (2013.01); H01L 21/28518 (2013.01); H10D 30/601 (2025.01); H10D 64/62 (2025.01); H10D 64/663 (2025.01)] 20 Claims
OG exemplary drawing
 
1. A method, comprising:
forming a gate structure over a substrate, the gate structure comprising a gate dielectric layer and a gate electrode over the gate dielectric layer;
forming a first gate spacer and a second gate spacer on opposite sidewalls of the gate structure, respectively;
implanting a first dopant of a first conductivity type into the substrate to form a lightly doped source region adjacent to the first gate spacer, and a lightly doped drain region adjacent to the second gate spacer;
forming a patterned mask, in a first process step, over a first portion of the lightly doped drain region, while leaving a second portion of the lightly doped drain region exposed, wherein the patterned mask and the gate dielectric layer are both in contact with the lightly doped drain region, and an entirety of the patterned mask is formed of a different material than the gate dielectric layer;
with the patterned mask in place, implanting a second dopant of the first conductivity type into the substrate, resulting in converting the second portion of the lightly doped drain region into a drain region, and converting a portion of the lightly doped source region into a source region, wherein a remainder of the lightly doped source region non-overlaps with the first gate spacer, and a boundary between the source region and the remainder of the lightly doped source region is laterally offset from an inner sidewall of the first gate spacer to a position directly below the gate structure, but a remainder of the lightly doped drain region overlaps with an entirety of the second gate spacer;
removing the patterned mask from the first portion of the lightly doped drain region;
after removing the patterned mask, forming a patterned silicide blocking layer, in a second process step separated from the first process step, over the first portion of the lightly doped drain region; and
after removing the patterned mask and forming the patterned silicide blocking layer, performing a silicidation process to form a silicide region on the drain region.