US 12,382,642 B1
Nonvolatile memory device including dual memory layers
Zhiqiang Wei, Pleasanton, CA (US); Zihui Wang, Mountain View, CA (US); Ebrahim Abedifard, San Jose, CA (US); and Yiming Huai, Pleasanton, CA (US)
Assigned to Avalanche Technology, Inc., Fremont, CA (US)
Filed by Avalanche Technology, Inc., Fremont, CA (US)
Filed on Mar. 22, 2025, as Appl. No. 19/087,510.
Application 19/087,510 is a division of application No. 18/106,159, filed on Feb. 6, 2023, granted, now 12,284,813.
Int. Cl. H10B 61/00 (2023.01); H01L 23/528 (2006.01); H10N 50/10 (2023.01)
CPC H10B 61/22 (2023.02) [H01L 23/5283 (2013.01); H10N 50/10 (2023.02)] 9 Claims
OG exemplary drawing
 
1. A nonvolatile memory device comprising:
a plurality of transistor pairs arranged in a rectangular array, each transistor pair including one of a plurality of first transistors and one of a plurality of second transistors that respectively include first and second drains and share one of a plurality of common sources;
an array of first memory elements and an array of second memory elements formed at different levels with respect to the plurality of transistor pairs, each first memory element and each second memory element being electrically connected to a respective first drain and a respective second drain, respectively;
a first plurality of first conductive lines extending along a first direction and configured to control current flow in the plurality of first transistors;
a second plurality of first conductive lines extending along the first direction and configured to control current flow in the plurality of second transistors;
a plurality of second conductive lines electrically connected to the array of first memory elements and the array of second memory elements along a second direction substantially perpendicular to the first direction; and
a plurality of third conductive lines electrically connected to the plurality of common sources along the first direction.