| CPC H10B 51/20 (2023.02) [H10B 51/10 (2023.02); H10D 62/115 (2025.01)] | 20 Claims |

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1. A memory device comprising:
a layer stack over a substrate, the layer stack comprising alternating layers of word lines (WLs) and a first dielectric material;
a second dielectric material embedded in the layer stack and extending vertically in the layer stack along a direction from an upper surface of the layer stack distal from the substrate to a lower surface of the layer stack facing the substrate;
a source line (SL) and a bit line (BL) in the second dielectric material and extending vertically through the layer stack;
a memory film between the layer stack and the second dielectric material; and
a channel layer between the memory film and the second dielectric material, wherein a first portion of the channel layer is disposed between the memory film and the SL, a second portion of the channel layer is disposed between the memory film and the BL, and a third portion of the channel layer is disposed laterally between the first portion of the channel layer and the second portion of the channel layer, wherein the first portion of the channel layer and the second portion of the channel layer comprise a crystalline channel material, and the third portion of the channel layer comprises an amorphous channel material.
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