US 12,382,634 B2
Semiconductor memory device that includes a plurality of first pillars, second pillars, and third pillars
Takahito Nishimura, Kuwana (JP); and Takuya Nishikawa, Yokkaichi (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 15, 2022, as Appl. No. 17/840,686.
Claims priority of application No. 2021-204989 (JP), filed on Dec. 17, 2021.
Prior Publication US 2023/0200071 A1, Jun. 22, 2023
Int. Cl. H10B 43/27 (2023.01); H10B 41/42 (2023.01)
CPC H10B 43/27 (2023.02) [H10B 41/42 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor memory device comprising:
a first stacked body that includes a plurality of conductive layers and a plurality of first insulating layers alternately stacked one by one and includes a memory region, a stepped region, and a connection region arranged in a first direction intersecting a stacking direction of the plurality of conductive layers;
a contact portion that is disposed in the connection region and electrically connects structures disposed above and below the first stacked body to each other;
a plurality of first pillars that is disposed in the memory region, extends in the first stacked body in the stacking direction, and forms a memory cell at each intersection with at least a part of the plurality of conductive layers;
a plurality of second pillars that includes a second insulating layer, has a layer structure different from a layer structure of the first pillars, and extends in the stacking direction in a position overlapping a stepped portion disposed in the stepped region, in the stacking direction, the plurality of conductive layers being processed in a stepped shape in the stepped portion; and
a plurality of third pillars that extends in the first stacked body in the stacking direction and has a same layer structure as the layer structure of the first pillars, at least a part of the plurality of third pillars being disposed in the connection region.