| CPC H10B 43/20 (2023.02) [G11C 5/063 (2013.01); H10B 43/35 (2023.02)] | 20 Claims |
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1. A memory device comprising:
a substrate;
a plurality of first conductor layers aligned apart from each other in a first direction;
a second conductor layer and a third conductor layer each extending in a second direction intersecting the first direction between the substrate and the plurality of first conductor layers, the second conductor layer and the third conductor layer being aligned apart from each other in the second direction;
a plurality of fourth conductor layers aligned apart from each other in the first direction on an opposite side of the substrate with respect to the plurality of first conductor layers;
a fifth conductor layer extending in the second direction between the plurality of first conductor layers and the plurality of fourth conductor layers;
a first memory pillar extending in the first direction, intersecting the plurality of first conductor layers, and coupled to the second conductor layer or the third conductor layer;
a second memory pillar extending in the first direction, intersecting the plurality of fourth conductor layers, and coupled to the fifth conductor layer; and
a first interconnect coupling between the fifth conductor layer and the substrate,
wherein the first interconnect includes a contact extending in the first direction and passing through the plurality of first conductor layers between the second conductor layer and the third conductor layer.
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