US 12,382,630 B2
Semiconductor assemblies including combination memory and methods of manufacturing the same
Jing Cheng Lin, Taichung (TW)
Assigned to Micron Technology, Inc., Boise, ID (US)
Filed by Micron Technology, Inc., Boise, ID (US)
Filed on Mar. 20, 2023, as Appl. No. 18/123,876.
Application 18/123,876 is a continuation of application No. 17/124,072, filed on Dec. 16, 2020, granted, now 11,610,911.
Claims priority of provisional application 62/958,159, filed on Jan. 7, 2020.
Prior Publication US 2023/0232622 A1, Jul. 20, 2023
Int. Cl. H01L 41/27 (2013.01); G11C 14/00 (2006.01); H01L 21/50 (2006.01); H01L 23/14 (2006.01); H01L 23/538 (2006.01); H01L 25/065 (2023.01); H10B 12/00 (2023.01); H10B 41/27 (2023.01); H10B 43/27 (2023.01)
CPC H10B 41/27 (2023.02) [G11C 14/0018 (2013.01); H01L 21/50 (2013.01); H01L 23/14 (2013.01); H01L 23/5384 (2013.01); H01L 23/5386 (2013.01); H01L 25/0657 (2013.01); H10B 12/30 (2023.02); H10B 43/27 (2023.02)] 20 Claims
OG exemplary drawing
 
1. A semiconductor package, comprising:
a die stack, the die stack including:
at least one volatile memory die;
at least one non-volatile (NV) memory die including a NV memory die; and
a controller device attached to the die stack, the controller device configured to provide an interface between the die stack and an external processor,
wherein the at least one volatile memory die includes a volatile memory die with through-silicon-vias (TSVs) coupled to the controller device and coupled to the NV memory die.