| CPC H10B 20/60 (2023.02) [H01L 21/26513 (2013.01); H10D 62/83 (2025.01); H10D 64/01 (2025.01); H10D 64/62 (2025.01)] | 14 Claims |
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1. A semiconductor device, comprising:
a semiconductor substrate;
a doped region formed in the semiconductor substrate;
a first source/drain and a second source/drain formed in the doped region;
a first conductive pad formed on the first source/drain and a second conductive pad formed on the second source/drain;
a gate dielectric layer disposed over the semiconductor substrate and the doped region exposing the first conductive pad and the second conductive pad;
a gate formed on the gate dielectric layer;
an insulation layer formed over the gate, the gate dielectric layer, the first conductive pad, and the second conductive pad; and
a first contact formed in the insulation layer in electric contact with the first conductive pad and a second contact formed in the insulation layer in electric contact with the second conductive pad,
wherein a first entire area of the first conductive pad is fully within a second area of the first source/drain, and a third entire area of the second conductive pad is fully within a fourth area of the second source/drain, and
wherein the first conductive pad fully overlaps the first source/drain, and the second conductive pad fully overlaps the second source/drain.
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