US 12,382,627 B2
Semiconductor structure and forming method thereof
Guangsu Shao, Hefei (CN); and Deyuan Xiao, Hefei (CN)
Assigned to CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed by CHANGXIN MEMORY TECHNOLOGIES, INC., Hefei (CN)
Filed on Sep. 23, 2022, as Appl. No. 17/934,679.
Claims priority of application No. 202210832052.X (CN), filed on Jul. 15, 2022.
Prior Publication US 2024/0023317 A1, Jan. 18, 2024
Int. Cl. H10B 12/00 (2023.01)
CPC H10B 12/482 (2023.02) [H10B 12/05 (2023.02); H10B 12/315 (2023.02)] 12 Claims
OG exemplary drawing
 
1. A forming method of a semiconductor structure, comprising:
providing a base, wherein the base is provided with a plurality of bit line isolation trenches extending along a first direction and an isolation structure located in the bit line isolation trench;
performing a patterned etching on the base to form a plurality of word line isolation trenches extending along a second direction, wherein the plurality of bit line isolation trenches and the plurality of word line isolation trenches form a plurality of semiconductor pillars in the base; and
forming a bit line metal layer on a surface of the semiconductor pillar under the word line isolation trench, the bit line metal layer surrounding a sidewall of the semiconductor pillar;
forming a first sacrificial layer in the word line isolation trench and on the bit line metal layer;
partially removing the first sacrificial layer to expose the semiconductor pillar; and
forming a word line gate structure on a surface of the exposed semiconductor pillar, wherein the word line gate structure surrounds the sidewall of the semiconductor pillar;
wherein
the performing a patterned etching on the base to form a plurality of word line isolation trenches extending along a second direction, a mask layer structure is formed on the base, and the mask layer structure is partially retained after the word line isolation trenches are formed, to form a support mask layer, wherein the support mask layer exposes the word line isolation trench;
the partially removing the first sacrificial layer to expose the semiconductor pillar comprises:
forming side walls on sidewalls of the support mask layer, wherein an opening exposing the first sacrificial layer is formed between adjacent side walls; and
partially removing the first sacrificial layer along the opening between the side walls; and
the forming a word line gate structure comprises:
forming a word line gate dielectric layer on the surface of the exposed semiconductor pillar;
forming an initial word line gate layer on a surface of the word line gate dielectric layer;
etching the initial word line gate layer by the support mask layer and the side walls as a mask to form word line gate layers, wherein a word line isolation opening is formed between adjacent word line gate layers, and the word line gate layer and the word line gate dielectric layer jointly form the word line gate structure; and
removing the support mask layer and the side walls.