| CPC H10B 12/312 (2023.02) [H10B 12/09 (2023.02); H10B 12/482 (2023.02)] | 20 Claims |
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1. A semiconductor memory device comprising:
a cell substrate;
a mold structure comprising a plurality of gate electrodes stacked on the cell substrate, the gate electrodes comprising a first ground selection line, a second ground selection line, and a plurality of word lines, which are sequentially stacked;
a channel structure that extends in a vertical direction, and penetrates the mold structure, the vertical direction crossing an upper surface of the cell substrate;
a partial isolation region that extends in a first direction that is parallel with the upper surface of the cell substrate and partially separates the mold structure; and
a ground isolation structure that connects two partial isolation regions adjacent to each other in the first direction, extends in the vertical direction, and penetrates the first ground selection line and the second ground selection line,
wherein a width of the ground isolation structure increases with distance from the cell substrate.
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