| CPC H10B 12/30 (2023.02) [H10B 12/10 (2023.02); H10B 12/20 (2023.02); H10B 99/10 (2023.02); H10B 99/22 (2023.02)] | 15 Claims |
|
1. A semiconductor structure, comprising:
a substrate;
a dielectric layer arranged on the substrate; and
a plurality of memory cell layers, the plurality of memory cell layers being spaced in the dielectric layer along a first direction, projections of any two adjacent of the plurality of memory cell layers on the substrate being overlapped, each of the plurality of memory cell layers comprising a plurality of memory cells spaced along a second direction, each of the plurality of memory cells comprising a first transistor and a second transistor connected to the first transistor, a first source, a first channel and a first drain of the first transistor being arranged along a third direction, the third direction and the substrate being parallel to each other, the first direction, the second direction and the third direction being perpendicular to one another, and the second direction and the third direction being positioned in a same horizontal plane;
wherein the first transistor is a columnar transistor, the first transistor further comprising a first gate and a first gate oxide layer, the first gate oxide layer and the first channel sequentially surrounding a portion of the first gate, and the first source and the first drain being spaced on the first channel;
wherein the second transistor is a columnar transistor, the second transistor comprising a second gate, a second channel, a second source, a second drain and a second gate oxide layer; the second source being electrically connected to an exposed portion of the first gate; and
the second gate oxide layer and the second channel sequentially surround a portion of the second gate, the second source and the second drain being spaced on the second channel.
|