| CPC H04W 72/04 (2013.01) [H04L 1/1812 (2013.01); H04L 5/0053 (2013.01); H04W 4/06 (2013.01); H04W 72/0466 (2013.01); H04L 12/189 (2013.01)] | 28 Claims |

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1. A communication device comprising:
a processor circuit and a memory circuit, wherein the memory is arranged to store instructions for the processor circuit,
wherein the processor circuit is arranged to receive at least one information units from a plurality of second communication devices,
wherein the processor circuit is arranged to receive at least one resource allocation message from a third communication device,
wherein the at least one resource allocation message defines an allocation of bit positions associated with an acknowledgement of the at least one information units in a combined acknowledgement information unit,
wherein the processor circuit is arranged to transmit a combined acknowledgement information unit in response to a reception of the at least one information units using the allocation of bit positions defined in the at least one resource allocation message.
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