US 12,382,167 B2
Control apparatus, control method, image capturing apparatus, and image capturing system
Shigeyoshi Ito, Tokyo (JP)
Assigned to CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed by CANON KABUSHIKI KAISHA, Tokyo (JP)
Filed on Jan. 27, 2023, as Appl. No. 18/160,368.
Application 18/160,368 is a continuation of application No. 17/123,020, filed on Dec. 15, 2020, granted, now 11,595,571.
Claims priority of application No. 2019-228616 (JP), filed on Dec. 18, 2019.
Prior Publication US 2023/0171489 A1, Jun. 1, 2023
This patent is subject to a terminal disclaimer.
Int. Cl. H04N 23/66 (2023.01); H04N 23/60 (2023.01); H04N 23/63 (2023.01)
CPC H04N 23/665 (2023.01) [H04N 23/63 (2023.01)] 16 Claims
OG exemplary drawing
 
1. A control apparatus comprising:
a generation unit that generates a first synchronization signal to be provided to an image sensor for controlling readout timing of an image signal from the image sensor and a second synchronization signal to be provided to a display for controlling timing for displaying an image based on the readout image signal on the display; and
a control unit that controls the generation unit,
wherein the control unit controls the generation unit such that
the first synchronization signal is repeatedly generated so as to read out a first image signal of each frame from the image sensor and the second synchronization signal is repeatedly generated so as to sequentially display images based on the first image signal on the display, the first synchronization signal and the second synchronization signal being generated with a predetermined time difference, and
in a case where a shooting instruction is given by a user's operation and a second image signal is read out from the image sensor at a timing corresponding to the shooting instruction between readouts of the first image signal of frames, the predetermined time difference between the first synchronization signal and the second synchronization signal is maintained before and after the readout of the second image signal by changing the output timings of the first synchronization signal and the second synchronization signal based on a preparation period for acquiring the second image signal and a charge accumulation period for the second image signal, and
wherein each unit is implemented by one or more processors, circuitry or a combination thereof.