US 12,382,130 B2
Systems and methods for decoding multiple symbols per clock cycle
Ka-Shu Ko, San Ramon, CA (US); and Abheek Banerjee, Palo Alto, CA (US)
Assigned to Apple Inc., Cupertino, CA (US)
Filed by Apple Inc., Cupertino, CA (US)
Filed on Jan. 8, 2024, as Appl. No. 18/407,151.
Claims priority of provisional application 63/538,004, filed on Sep. 12, 2023.
Prior Publication US 2025/0088707 A1, Mar. 13, 2025
Int. Cl. H04N 21/44 (2011.01); G06F 1/03 (2006.01); H04N 21/4402 (2011.01)
CPC H04N 21/4402 (2013.01) [G06F 1/03 (2013.01); H04N 21/44008 (2013.01)] 21 Claims
OG exemplary drawing
 
1. An electronic device, comprising:
a video parser configured to receive an encoded video bitstream; and
a video decoder configured to receive the encoded video bitstream from the video parser and decode the encoded video bitstream, the video decoder comprising:
a cumulative distribution function (CDF) lookup table; and
multiple symbol decoders sharing access to the CDF lookup table and configured to use the CDF lookup table to decode multiple coefficient base symbols per clock cycle.