US 12,381,570 B2
Semiconductor integrated circuit and receiver device
Huy Cu Ngo, Isehara Kanagawa (JP)
Assigned to Kioxia Corporation, Tokyo (JP)
Filed by Kioxia Corporation, Tokyo (JP)
Filed on Jun. 13, 2023, as Appl. No. 18/209,380.
Claims priority of application No. 2022-145575 (JP), filed on Sep. 13, 2022.
Prior Publication US 2024/0097699 A1, Mar. 21, 2024
Int. Cl. H03M 1/00 (2006.01); H03M 1/14 (2006.01); H03M 1/46 (2006.01); H03M 1/12 (2006.01)
CPC H03M 1/466 (2013.01) [H03M 1/14 (2013.01); H03M 1/462 (2013.01); H03M 1/121 (2013.01)] 18 Claims
OG exemplary drawing
 
1. A semiconductor integrated circuit comprising:
a first converter configured to determine a first bit string from an analog signal based on a first clock signal;
a second converter configured to determine a second bit string from the analog signal based on a second clock signal shifted from the first clock signal by a first phase; and
a circuit configured to supply a reference voltage to the first converter and the second converter, wherein
the circuit includes:
a first capacitor;
a second capacitor;
a third capacitor;
a first switching element;
a second switching element;
a first buffer including: an input end to which a voltage corresponding to the reference voltage is supplied; and an output end coupled to the first capacitor, a first end of the first switching element, and a first end of the second switching element;
a second buffer including: an input end to which the voltage corresponding to the reference voltage is supplied; and an output end coupled to the second capacitor, a second end of the first switching element, and the first converter; and
a third buffer including: an input end to which the voltage corresponding to the reference voltage is supplied; and an output end coupled to the third capacitor, a second end of the second switching element, and the second converter.