CPC H03M 1/1033 (2013.01) [G04F 10/005 (2013.01); H03K 5/13 (2013.01); H03K 2005/00019 (2013.01)] | 21 Claims |
1. An apparatus comprising:
a multi-modulus (MM) divider having a clock input, a first divisor input and a MM divider output;
a delta-sigma modulator having a second divisor input, a divisor output and a residual output, the divisor output coupled to the first divisor input;
a digital-to-time converter (DTC) having a DTC clock input, a DTC control input, a DTC calibration input, and a DTC output; and
a processing circuit having a residual input, a main code output, and a correction code output, the residual input coupled to the residual output, the main code output coupled to the DTC control input, and the correction code output coupled to the DTC calibration input.
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