CPC H03L 7/1976 (2013.01) [H03L 7/195 (2013.01)] | 20 Claims |
1. A semiconductor device comprising:
a first timing channel formed by an analog phase lock loop (APLL), a first digital phase lock loop (DPLL) and a first summation module; and
a second timing channel formed by a fractional output divider (FOD), a second digital phase lock loop (DPLL) and a second summation module, wherein:
the first summation module is configured to:
apply at least one operand on one or more of:
a first fractional frequency offset signal being outputted by the first DPLL, wherein the first fractional frequency offset signal is based on a feedback fractional frequency offset signal and a feedback of a first clock signal being outputted by the APLL, and the feedback fractional frequency offset signal is variable; and
a second fractional frequency offset signal being outputted by the second DPLL; and
sum results of the application of the at least one operand by the first summation module to generate a first signal that controls a frequency of the first clock signal being outputted by the APLL; and
the second summation module is configured to:
apply the at least one operand on one or more of:
the first fractional frequency offset signal being outputted by the first DPLL; and
the second fractional frequency offset signal being outputted by the second DPLL; and
sum results of the application of the at least one operand by the second summation module to generate a second signal that controls a frequency of a second clock signal being outputted by the FOD.
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