US 12,381,556 B2
Kickback reduction in bootstrapped switches
Lei Sun, San Diego, CA (US); Elias Dagher, Laguna Niguel, CA (US); and Dinesh Jagannath Alladi, San Diego, CA (US)
Assigned to QUALCOMM Incorporated, San Diego, CA (US)
Filed by QUALCOMM Incorporated, San Diego, CA (US)
Filed on Mar. 9, 2023, as Appl. No. 18/181,026.
Prior Publication US 2024/0305296 A1, Sep. 12, 2024
Int. Cl. H03K 19/003 (2006.01); H03K 17/06 (2006.01); H03K 17/687 (2006.01); H03K 19/017 (2006.01)
CPC H03K 19/00361 (2013.01) [H03K 17/063 (2013.01); H03K 17/6871 (2013.01); H03K 19/01735 (2013.01)] 29 Claims
OG exemplary drawing
 
1. A system, comprising:
a switch transistor;
a bootstrap circuit having an input and an output, wherein the output of the bootstrap circuit is coupled to a gate of the switch transistor;
a first buffer having an input and an output, wherein the output of the first buffer is coupled to a terminal of the switch transistor, the first buffer comprising:
a first transistor having a gate, a source, and a drain, wherein the gate of the first transistor is coupled to the input of the first buffer, the drain of the first transistor is coupled to a first rail, and the source of the first transistor is coupled to the output of the first buffer; and
a first load coupled between the output of the first buffer and a second rail; and
a second buffer having an input and an output, wherein the input of the second buffer is coupled to the input of the first buffer, and the output of the second buffer is coupled to the input of the bootstrap circuit.