US 12,381,520 B2
Method and circuit to isolate body capacitance in semiconductor devices
Garming Liang, Hsin-Chu (TW); Simon Chai, Hsin-Chu (TW); Tzu-Jin Yeh, Hsinchu (TW); En-Hsiang Yeh, Hsin-Chu (TW); and Wen-Sheng Chen, Taipei (TW)
Assigned to TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD., Hsinchu (TW)
Filed by Taiwan Semiconductor Manufacturing Co., Ltd., Hsin-Chu (TW)
Filed on Nov. 17, 2023, as Appl. No. 18/513,103.
Application 18/513,103 is a continuation of application No. 18/081,513, filed on Dec. 14, 2022, granted, now 11,855,590.
Application 18/081,513 is a continuation of application No. 16/673,765, filed on Nov. 4, 2019, granted, now 11,558,019.
Claims priority of provisional application 62/767,734, filed on Nov. 15, 2018.
Prior Publication US 2024/0088842 A1, Mar. 14, 2024
This patent is subject to a terminal disclaimer.
Int. Cl. H03F 1/22 (2006.01); H03F 1/02 (2006.01); H03F 3/21 (2006.01); H10D 84/80 (2025.01); H10D 84/85 (2025.01)
CPC H03F 3/211 (2013.01) [H03F 1/0205 (2013.01); H10D 84/811 (2025.01); H10D 84/859 (2025.01); H03F 1/223 (2013.01); H03F 2200/451 (2013.01); H03F 2200/72 (2013.01); H03F 2200/75 (2013.01)] 20 Claims
OG exemplary drawing
 
1. An amplifying circuit, comprising:
a common-gate (CG) amplifier, wherein the CG amplifier comprises a first transistor, wherein
a source terminal and a body terminal of the first transistor are coupled together through a first diode, wherein the first diode is formed between an N region of the source terminal of the first transistor and a P-well region in which the body terminal of the first transistor is fabricated, and
a drain terminal and the body terminal of the first transistor are coupled together through a second diode; and
a common-source (CS) amplifier, wherein the CS amplifier comprises a second transistor connected in series with the first transistor, wherein the second transistor is further configured to receive an input voltage at a gate terminal of the CS amplifier.