US 12,381,513 B2
IQ phase imbalance calibration using sampling clock delay adjustment
Xiaozhe Fan, Colchester, VT (US); and Mustapha Slamani, South Burlington, VT (US)
Assigned to GlobalFoundries U.S. Inc., Malta, NY (US)
Filed by GlobalFoundries U.S. Inc., Malta, NY (US)
Filed on Dec. 18, 2023, as Appl. No. 18/543,416.
Prior Publication US 2025/0202428 A1, Jun. 19, 2025
Int. Cl. H03D 3/02 (2006.01); H03D 3/00 (2006.01)
CPC H03D 3/008 (2013.01) 19 Claims
OG exemplary drawing
 
1. A system for phase imbalance calibration, comprising:
an in-phase (I) signal channel including an analog-to-digital converter (ADC) for sampling an I signal to provide a sampled I signal;
a quadrature (Q) signal channel including an ADC for sampling a Q signal to provide a sampled Q signal;
a sampling clock for controlling the sampling of the ADC on the I signal channel and the sampling of the ADC on the Q signal channel; and
sampling clock delay circuitry for adjusting one of a sampling start time of the ADC on the I channel and a sampling start time of the ADC on the Q channel relative to one another such that the sampled I signal and the sampled Q signal are in phase.