US 12,381,179 B2
Modular low latency electrical sequence for die-to-die interface
Phaik Yi Chan, Bayan Lepas (MY); and Ting Ting Teh, San Jose, CA (US)
Assigned to Intel Corporation, Santa Clara, CA (US)
Filed by Intel Corporation, Santa Clara, CA (US)
Filed on Mar. 11, 2022, as Appl. No. 17/693,005.
Prior Publication US 2022/0199573 A1, Jun. 23, 2022
Int. Cl. H01L 25/00 (2006.01); H01L 25/065 (2023.01)
CPC H01L 25/0652 (2013.01) [H01L 2225/06513 (2013.01)] 20 Claims
OG exemplary drawing
 
1. A system comprising:
a first die in a package, the first die comprising:
a first receiver and a first transmitter to couple to a link between the first die and a second die in the package, the second die comprising a second receiver and a second transmitter; and
circuitry to:
place the first receiver and first transmitter into isolation modes;
provide a first signal to the second die to request placement of the second transmitter into a deisolation mode;
place the first receiver and first transmitter into deisolation modes responsive to a second signal from the second die; and
provide a third signal to the second die to request placement of the second receiver into a deisolation mode.