US 12,381,167 B2
Semiconductor structure having vias with different dimensions
Shing-Yih Shih, New Taipei (TW); and Chih-Ching Lin, Taoyuan (TW)
Assigned to NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed by NANYA TECHNOLOGY CORPORATION, New Taipei (TW)
Filed on May 12, 2022, as Appl. No. 17/742,544.
Prior Publication US 2023/0369264 A1, Nov. 16, 2023
Int. Cl. H01L 23/00 (2006.01); H01L 21/768 (2006.01); H01L 23/48 (2006.01); H01L 23/528 (2006.01); H01L 23/535 (2006.01)
CPC H01L 24/08 (2013.01) [H01L 21/76805 (2013.01); H01L 21/76816 (2013.01); H01L 21/76831 (2013.01); H01L 21/76895 (2013.01); H01L 21/76898 (2013.01); H01L 23/481 (2013.01); H01L 23/5283 (2013.01); H01L 23/535 (2013.01); H01L 24/80 (2013.01); H01L 2224/08145 (2013.01); H01L 2224/80896 (2013.01)] 11 Claims
OG exemplary drawing
 
1. A semiconductor structure, comprising:
a first wafer including a first substrate, a first dielectric layer over the first substrate, and a first conductive pad surrounded by the first dielectric layer;
a second wafer including a second dielectric layer, a second substrate over the second dielectric layer, and a second conductive pad surrounded by the second dielectric layer;
a passivation disposed over the second substrate;
a first conductive via extending from the first conductive pad through the second wafer and the passivation, and having a first width surrounded by the second wafer, wherein the first conductive via has a uniform width, such that the first width is consistent from top to bottom;
a second conductive via extending from the second conductive pad through the passivation and the second substrate and partially through the second dielectric layer,
a first dielectric liner formed between the first conductive via and the second wafer, wherein the first dielectric liner has a top opening formed at a top surface of the passivation and a bottom opening formed at a top surface of the first conductive pad, such that the first conductive via is in contact with the top surface of the first conductive pad through the bottom opening of the first dielectric liner; and
a second dielectric liner formed between the second conductive via and the second wafer, wherein the second dielectric liner has a top opening formed at the top surface of the passivation and a bottom opening formed at a top surface of the second conductive pad;
wherein the second conductive via has:
a first portion surrounded by the second substrate and having a second width which is a consistent width, wherein the first portion of the second conductive via is in contact with the top surface of the second conductive pad through the bottom opening of the second dielectric liner;
a second portion surrounded by the passivation and having a third width which is larger than the second width, wherein the third width is a consistent width; and
a tapered portion surrounded by the passivation, wherein the tapered portion has a tapered width gradually reduced from the third width of the second portion to the second width of the first portion,
wherein the second width is less than the first width.