US 12,381,119 B2
Seal for microelectronic assembly
Rajesh Katkar, San Jose, CA (US); Liang Wang, Milpitas, CA (US); Cyprian Emeka Uzoh, San Jose, CA (US); Shaowu Huang, Sunnyvale, CA (US); Guilian Gao, San Jose, CA (US); and Ilyas Mohammed, Santa Clara, CA (US)
Assigned to Adeia Semiconductor Bonding Technologies Inc., San Jose, CA (US)
Filed by ADEIA SEMICONDUCTOR BONDING TECHNOLOGIES INC., San Jose, CA (US)
Filed on Sep. 7, 2023, as Appl. No. 18/463,080.
Application 16/678,058 is a division of application No. 15/920,759, filed on Mar. 14, 2018, granted, now 10,508,030, issued on Dec. 17, 2019.
Application 18/463,080 is a continuation of application No. 17/806,253, filed on Jun. 9, 2022, granted, now 12,322,667.
Application 17/806,253 is a continuation of application No. 16/678,058, filed on Nov. 8, 2019, granted, now 11,417,576, issued on Aug. 16, 2022.
Claims priority of provisional application 62/474,478, filed on Mar. 21, 2017.
Prior Publication US 2023/0420313 A1, Dec. 28, 2023
Int. Cl. H01L 23/04 (2006.01); B81B 7/00 (2006.01); B81C 1/00 (2006.01); H01L 23/02 (2006.01); H01L 23/053 (2006.01); H01L 23/10 (2006.01)
CPC H01L 23/10 (2013.01) [B81B 7/0032 (2013.01); B81B 7/0074 (2013.01); B81C 1/00261 (2013.01); B81C 1/00269 (2013.01); B81C 1/00333 (2013.01); H01L 23/02 (2013.01); H01L 23/04 (2013.01); H01L 23/053 (2013.01); B81C 2203/038 (2013.01)] 24 Claims
OG exemplary drawing
 
1. A bonded structure, comprising:
a first microelectronic component comprising a first surface and a second surface opposite the first surface, wherein the first surface comprises a first dielectric and a first conductive feature;
a second microelectronic component comprising a third surface comprising a second dielectric and a second conductive feature, wherein the first surface is in contact with the third surface to form a bond joint, and wherein the bond joint comprises a dielectric-to-dielectric direct bond between the first dielectric and the second dielectric and a metal-to-metal direct bond between the first conductive feature and the second conductive feature; and
a channel extending continuously around an interior region of the bonded structure, wherein a height of the channel extends at least across the bond joint, the channel having sidewalls at least partially covered with metal, the sidewalls extending from the second surface into the first microelectronic component.